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ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 1 - htc features z two linear regulators - maximum 2a current from vddq - source and sink up to 2a vtt current z 1.7v to 2.8v adjustable vddq output voltage z 0.85v to 1.4v vtt output voltage (tracking at 50% of vddq) z buffered vref output z 500mv typical vddq dropout voltage at 2a z excellent load and line regulation, low noise z meets jedec ddr-i and ddr-ii memory power spec z linear regulator design requires no inductors and has low external component count z integrated power mosfets z dual purpose adj/shutdown pin z enable vtt pin for sleep or suspend to ram function z built-in over-current limit and thermal shutdown for vddq and vtt z fast transient response z low quiescent current application z ddr memory and active termination buses z desktop computers, servers z residential and enterprise gateways z dsl modems z routers and switches z dvd recorders, lcd tv and stb z 3d agp cards descripsion tdfn-8 pkg sop-8 pkg sop-16 pkg ordering information device package TJ3212q tdfn-8 TJ3212dp sop-8 TJ3212d sop-16 the TJ3212 is a dual-output low noise linear regulator designed to meet sstl-2 and sstl-3 specifications for ddr-sdram vddq supply and termination voltage vtt supply. with integrated power mosfets the TJ3212 can source up to 2a of vddq continuous current, and source or sink up to 2a vtt continuous current. the typical dropout voltage for vddq is 500mv at 2a load current. the TJ3212 provides excellent full load regulation and fast response to transient load changes. it also has built- in over-current limits and thermal shutdown at 170c. the TJ3212 supports suspend-to-ram (str) and acpi co mpliance with shutdown mode which tri-states vtt to minimize quiescent system current. the TJ3212 is available in a space saving tdfn-8 and soic-8 surface mount packages. low thermal resistance allows them to withstand high power dissip ation at 85c ambient. the TJ3212 can operate over the industrial ambient temperature range of ?40c to 85c.
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 2 - htc ordering information package order no. description supplied as status tdfn-8 TJ3212q reel contact us sop-8 TJ3212dp reel contact us sop-16 TJ3212d tube contact us absolute maximum ratings characteristic symbol ratings unit v in to gnd [gnd - 0.3] to +6.0 v pin voltage v ddq , v tt to gnd [gnd - 0.3] to +6.0 v adjsd to gnd [gnd - 0.3] to +6.0 v output current v ddq / v tt , continuous (note 1) 2.0 / 2.0 a v ddq / v tt , peak 2.8 / 2.8 a v ddq source + v tt source 3 a operating ambient temperature t a ?40 to 85 c operating junction temperature t j ?40 to 170 c storage temperature t stg ?40 to 150 c thermal resistance (note 2) tdfn-8 sop-8 sop-16 r ja 55 120 90 c / w continuous power dissipation (note 2) t a = 25c / 85c tdfn-8 sop-8 sop-16 pd (cont.) 2.6 / 1.5 1.2 / 0.7 1.6 / 0.9 w lead temperature (soldering, 10sec) t sol 300 c esd protection (hbm) 2000 v
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 3 - htc operating ratings characteristic symbol ratings unit ambient operating temperature range t opr ?40 to 85 c v ddq regulator supply voltage, v in load current, continuous load current, peak (1 sec) c ddq 3.0 to 3.6 0 to 2 2.5 220 v a a uf v tt regulator supply voltage, v in load current, continuous load current, peak (1 sec) c tt 3.0 to 3.6 0 to 2.0 2.50 220 v a a uf operating ratings (continued) characteristic symbol ratings unit v in supply voltage range 3.0 to 3.6 v v ddq source + v tt source load current, continuous load current, peak (1 sec) 2.5 3.5 a a junction operating temperature range t jopr ?40 to +150 c
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 4 - htc pin configuration 8765 1234 1234 8765 5678 12 11 10 9 1234 16 15 14 13 tdfn-8 sop-8 sop-16 pin description pin no. tdfn-8 / sop-8 pkg sop-16 pkg name function name function 1 vin input supply vin input supply 2 vtt output voltage for connection to termination resistors vin input supply 3 gnd ground vin input supply 4 gnd ground n.c not internally connected. 5 en chip enable n.c not internally connected. 6 adj vddq adjust vtt output voltage for connection to termination resistors 7 vref reference voltage gnd ground 8 vddq vddq regulator output voltage gnd ground 9 - - en chip enable 10 - - sense feedback for regulating vtt 11 - - vref reference voltage 12 - - vddq vddq regulator output voltage 13 - - vddq vddq regulator output voltage 14 - - adj vddq adjust 15 - - gnd ground 16 - - vin input supply
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 5 - htc typical application 1 2 3 8 7 6 5 vin vtt gnd vddq vref adj gnd vddq = 2.5v/2a TJ3212 vin = 3.0v ~3.6v vtt = 1.25v/2a r2 12k r1 13k s/d 4 4.7uf (opt.) 220 uf 1.2v en 220 uf 220 uf 4.7uf (opt.) 4.7uf (opt.)
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 6 - htc electrical characteristics parameters symbol condition min. typ. max. unit supply voltage range v in 3.0 3.6 v quiescent current i q i ddq = 0, i tt =0 2 ma adjsd voltage v adjsd (3) 1.225 1.250 1.275 v shutdown current i shdn v adjsd = 3.3v (shutdown) 0.1 ma adjsd logic high shdn_h (2) 2.7 v adjsd logic low shdn_l (3) 1.5 v under-voltage lockout uvlo hysteresis = 100mv (3) 2.40 2.70 2.90 v thermal shdn threshold t over (3) 150 170 c thermal shdn hysteresis t hys 50 c v ddq , v tt tempco tempco i out = 1a (3) 100 ppm/c vddq regulator vddq output voltage v ddq edf i ddq = 100ma 2.450 2.500 2.550 v vddq load regulation v ddq load 10ma i ddq 2a (4) 10 25 mv vddq line regulator v ddq line 3.0v v in 3.6v, i ddq = 0.1a 5 25 mv vddq dropout voltage v drop i ddq = 2a (5) 500 mv adjsd bias current i adj (3) 0.8 3 ua vddq current limit i ddq lim 2.0 2.5 a vtt regulator vtt output voltage v tt def i tt = 100ma 1.225 1.250 1.275 v vtt load regulation v tt load source, 10ma i tt 2a (4) sink, -2a i tt 10ma (4) -30 10 -10 30 mv mv vtt line regulator v tt line 3.0v v in 3.6v, i tt = 0.1a 5 15 mv itt current limit i tt lim source / sink (4) 2.0 2.5 a vtt shutdown leakage current i vtt off v en_vtt = 0.4v (shutdown) 10 ua reference voltage v ref c ref = 0.1uf, i ref = 100ua 1.225 1.250 1.275 v note 1. vin = 3.3v, vddq = 2.50v, vtt = 1.25v (default values), cddq=ctt=47 f, ta = 25c unless otherwise specified. note 2. the adjsd logic high value is normally satisfied for fu ll input voltage range by using a low leakage current (below 1 a). schottky diode at adjsd control pin. note 3. guaranteed by design. note 4. load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. fo r high current tests, correlation method can be used. changes in output voltage du e to heating effects must be taken into account separately. load and line regulation values are guaranteed by des ign up to the maximum power dissipation. note 5. dropout voltage is the input to output voltage differential at which output voltage has dropped 100mv from the nominal value obtained at 3.3v input. it depends on load current and junction temperature. guaranteed by design.
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 7 - htc typical operating characteristics vtt vs. vddq vddq vs. iddq vddq dropout vs. iddq vtt vs. load current
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 8 - htc typical operating characteristics (continued) vddq transient response vtt transient response softstart into full load
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 9 - htc application information powering ddr memory double-data-rate (ddr) memory has provided a huge st ep in performance for personal computers, servers and graphic systems. as is apparent in its name, ddr operat es at double the data rate of earlier ram, with two memory accesses per cycle versus one. ddr sdrams transmit data at bot h the rising and falling edges of the memory bus clock. ddr?s use of stub series terminated logic (sstl) topolog y improves noise immunity and power-supply rejection, while reducing power dissipation. to achieve this performance improvement, ddr requires more complex power management architecture than previous ram technology. unlike the conventional dram technology, ddr sdram uses differential inputs and a reference voltage for all interface signals. this increases the data bus bandwid th, and lowers the system power consumption. power consumption is reduced by lower operating voltage, a lo wer signal voltage swing asso ciated with stub series terminated logic (sstl_2), and by the use of a termination voltage, v tt . sstl_2 is an industry standard defined in jedec document jesd8-9. sstl_2 maintains high-spe ed data bus signal integrity by reducing transmission reflections. jedec further defines the ddr sdram specification in jesd79c. ddr memory requires three tightly regulated voltages: v ddq , v tt , and v ref (see figure 1). in a typical sstl_2 receiver, the higher current v ddq supply voltage is normally 2.5v with a tolerance of 200mv. the active bus termination voltage, v tt , is half of v ddq . v ref is a reference voltage that tracks half of v ddq 1%, and is compared with the v tt terminated signal at the receiver. v tt must be within 40mv of v ref . figure 1. typical ddr terminations, class ii the v tt power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. in a typi cal ddr data bus system each data line termination may momentarily consume 16.2ma to achieve the 405mv minimum over v tt needed at the receiver: 16.2ma = ) ? (25 r 405mv = i t n terminatio a typical 64mbyte sstl-2 memory system, with 128 terminated lines, has a worst-case maximum v tt supply current up to 2.07a. however, a ddr memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. these high current peaks can be handled by the v tt external capacitor. in a real memory system, the continuous average v tt current level in normal operation is less than 200ma.
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 10 - htc the v ddq power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. the current level typically stays within a range of 0.5a to 1a, with peaks up to 2a or more, depending on memory size and the computing operations being performed. the tight tracking requirements and the need for v tt to sink, as well as source, current provide unique challenges for powering ddr sdram. TJ3212 regulator the TJ3212 dual output linear regulator provides all of the power requirement s of ddr memory by combining two linear regulators into a single package. v ddq regulator can supply up to 2a current, and the two quadrant v tt termination regulator has current sink and source capability to 2a. the v ddq linear regulator uses a pmos pass element for a very low dropout voltage, typically 500mv at a 2a output. the output voltage of v ddq can be set by an external voltage divider. the use of regulat ors for both the upper and lower side of the v ddq output allows a fast transient response to any change of the load, from hi gh current to low current or inversely. the second output, v tt , is regulated at v ddq / 2 by an internal resistor divider. same as v ddq , v tt has the same fast transient response to load change in both directions. the v tt regulator can source, as well as sink, up to 2a current. the TJ3212 is designed for optimal operation from a nominal 3.3v dc bus, but can work with v in up to 5v. when operating at higher v in voltages, attention must be given to t he increased package power dissipation and proportionally increased heat generati on. limited by the package thermal re sistance, the maximum output current of the device at higher v in cannot exceed the limit imposed by t he maximum power dissipation value. v ref is typically routed to inputs with high impedance, such as a comparator, with little current draw. an adequate v ref can be created with a simple voltage divider of precision, matched resistors from v ddq to ground. a small ceramic bypass capacitor can also be added for improved noise performance. input and output capacitors the TJ3212 requires that at least a 220uf elec trolytic capacitor be located near the v in pin for stability and to maintain the input bus voltage during load transients. an additional 4.7uf ceramic capacitor between the v in and gnd, located as close as possible to thos e pins, is recommended to ensure stability. at a minimum, a 220uf electrolytic capacitor is recommended for the v ddq output. an additional 4.7uf ceramic capacitor between the v ddq and gnd, located very close to those pins, is recommended. at a minimum, a 220uf electrolytic capacitor is recommended for the v tt output. this capacitor should have low esr to achieve best output transient response. sp or os con capacitors provide low esr at high frequency, and thus are a good choice. in addition, plac e a 4.7uf ceramic capacitor between the v tt pin and gnd, located very close to those pins. the total esr must be low enough to keep the transient within the v tt window of 40mv during the transition for source to sink. an average current step of 0.5a requires: ? m 40 = a 1 mv 40 < esr both outputs will remain stable and in regulation even during light or no load conditions. the general recommendation for circuit stability for the TJ3212 requires the following: 1) c in = c ddq = c tt = 220uf / 4.7uf for the full temperature range of ?40 to +85 c . 2) c in = c ddq = c tt = 100uf / 2.2uf for the temperature range of ?25 to +85 c .
ddr vddq and vtt termination voltage regulator TJ3212 mar. 2011 - preliminary - 11 - htc adjusting vddq output voltage the TJ3212 internal bandgap reference is set at 1.25v. the v ddq voltage is adjustable by using a resistor divider, r1 and r2: 2 r 2 r + 1 r v = v adj ddq where v adj = 1.25v. the recommended divider value is r1 = r2 = 10k for ddr-1 application, and r1 = 4.42k, r2 = 10k for ddr-2 application (v ddq = 1.8v, v tt = 0.9v). shutdown adjsd also serves as a shutdown pin. when this is pulled high (shdn_h), both the v ddq and the v tt outputs tri- state and could sink/source less than 10ua . during shutdown, the quiescent current is reduced to less than 0.5ma, independent of output load. it is recommended that a low leakage schottky diode be placed between the adjsd pin and an external shutdown signal to prevent interference with the adj pin?s normal operation. when t he diode anode is pulled low, or left open, the TJ3212 is again enabled. for shutdown operation, observe the following: v ddq under adjsd shutdown condition, v ddq should go to tri-state. under en_vtt shutdown condition, v ddq should keep state (2.5v). v tt under adjsd or en_vtt shutdown condition, v tt should go to tri-state and should sink or source less than 10ua. v ref under adjsd shutdown condition, v ref should go to zero. under en_vtt shutdown condition, v ref should keep state (1.2v or vddq/2). current limit and over-temperature protection the TJ3212 features internal current limiting with thermal protection. during normal operation, v ddq limits the output current to approximately 2a and v tt limits the output current to approximately 2a. when v tt is current limiting into a hard short circuit, the output current folds ba ck to a lower level (~1a) unt il the over-current condition ends. while current limiting is designed to prevent gros s device failure, care should be taken not to exceed the power dissipation ratings of the packa ge. if the junction temperature of t he device exceeds 170c(typical), the thermal protection circuitry triggers and tri-states both v ddq and v tt outputs. once the junction temperature has cooled to below about 120c the TJ3212 returns to normal operation. typical thermal characteristics the overall junction to ambient thermal resistance ( ja ) for device power dissipation (pd) primarily consists of two paths in the series. the first path is the junction to the case ( jc ) which is defined by the package style and the second path is case to ambient ( ca ) thermal resistance which is dependent on board layout. the final operating junction temperature for any condition can be estimated by the following thermal equation: t j = t a + p d x ( jc ) + p d x ( ca ) = t a + p d x ( ca )

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